View AD5231BRUZ10_7003767.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nonvolatile memory, 1024 - position digital potentiometer data sheet ad5231 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any i nfringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and re gistered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2001 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures 1024- position resolution nonvolatile memory maintains wiper setting power - on refresh with eemem setting eemem restore time: 140 s typ full monotonic operation 1 0 k?, 50 k?, and 100 k? terminal resistance permanent memory write protection wiper se tting readback predefined linear increment/decrement instructions predefined 6 db/step log taper increment/decrement i n structions spi? - compatible serial interface 3 v to 5 v single - supply or 2.5 v dual - supply operation 28 bytes extra nonvolatile memory f or user - defined data 100- year typical data retention, t a = 55 c a pplications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage to current conversion programmable filters, delays, time constants programmable power supply low resolution dac replacement sensor calibration f unctional b lock d iagram eemem(0) eemem(1) ad5231 rdac clk sdi gnd sdo rdy sdo v dd v ss a w b o1 o2 sdi 2 pr wp cs addr decode rdac register digital register serial interface eemem control 28 bytes user eemem digital outout buffer 02739-001 figure 1. code (decimal) 100 75 0 0 1023 256 r wa (d), r wb (d); (% of nominal r ab ) 512 768 50 25 r wb r wa 02739-002 figure 2. r wa (d) and r wb (d) vs. decimal code g eneral d escription the ad5231 is a nonvolatile memory 1 , digitally controlled potentiomete r 2 with 1024 - step resolution. the device performs the same electronic adjustment function as a mechanical pote n tiometer with enhanced resolution, solid state reliability, and r e mote controllability. the ad5231 has versati le programming that uses a standard 3 - wire serial interface for 16 modes of operation and adjustment, including scratchpad programming, me m ory storing an d restoring, increment/decrement, 6 db/step log taper adjustment, wiper setting readback, and extra ee mem for user - defined information, such as memory data for other components, look - up table, or system identification i n formation . in scratchpad programming mode, a specific setting can be programmed directly to the rdac register that sets the resi s tance b e tween terminal s w C a and terminal s w C b. this setting can be stored into the eemem and is transferred automatically to the rdac register during system power - on. the eemem content can be restored dynamically or through external pr strob ing, and a wp function protects eemem contents. to simplify the p rogramming, the linear - step incr e ment or decrement commands can be used to move the rdac wiper up or down, one step at a time. the 6 db step co m mands can be used to do uble or half the rdac wiper setting. the ad5231 is available in a 16 - lead tssop. the part is guaranteed to operate over the extended industrial te m perature range of ?40c to +85c. 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital potentiometer and rdac are used interchangeably.
ad5231 data sheet rev. d | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 10 k?, 50 k?, 100 k? versions .. 3 timing ch aracteristics 10 k?, 50 k?, 100 k? versions ...... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 13 theory of operation ...................................................................... 14 scratchpad and eemem programming .................................. 14 basic ope ration .......................................................................... 14 eemem protection .................................................................... 14 digital input/output configuration ........................................ 15 serial data interface ................................................................... 15 daisy - chain operation ............................................................. 15 terminal voltage operation range ......................................... 16 power - up sequence ................................................................... 16 latched digital outputs ............................................................ 16 advanced control modes ......................................................... 18 rdac structure .......................................................................... 19 programming the variable resistor ......................................... 19 programming the potentiometer divider ............................... 20 programming examples ............................................................ 21 flash/eemem reliability .......................................................... 22 applicati ons ..................................................................................... 23 bipolar operation from dual supplies .................................... 23 high voltage operation ............................................................ 23 bipolar programmable gain amplifier ................................... 23 10- bit bipolar dac .................................................................... 23 10- bit unipolar dac ................................................................. 24 programmable voltage source with boosted output ........... 24 programmable current source ................................................ 24 programmable bidi rectional current source ......................... 25 resistance scaling ...................................................................... 25 rdac circuit simulation model ............................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 r evision h istory 3/13 rev. c to rev. d added t wp ; table 2 ............................................................................ 5 changes to ordering guide .......................................................... 27 1 /0 7 rev. b to rev. c updated format .................................................................. universal changes to dynamic characteristics specifications ..................... 4 changes to table 2 footnote ............................................................ 5 changes to table 3 ............................................................................. 7 changes to ordering guide ........................................................... 27 9 /04 rev. a to rev. b updated format .................................................................. universal changes to table 20 ......................................................................... 2 3 changes to resistance scaling section ......................................... 25 changes to ordering guide ........................................................... 27 5/04 rev. 0 to rev. a updated formatting ............................................................ universal edits to features, general description, and block diagram ....... 1 changes to specifications ................................................................. 3 replaced timing diagrams .............................................................. 6 changes to pin fu nction descriptions ........................................... 8 changes to typical performance characteristics .......................... 9 changes to test circuits ................................................................. 13 edits to theory of operation ......................................................... 14 edits to applications ....................................................................... 23 updated outline dimensions ........................................................ 27 12/01 revision 0: initial version
data sheet ad5231 rev. d | page 3 of 28 specifications electrical character istics 10 k ?, 50 k ?, 100 k ? versions v dd = 3 v 10% or 5 v 10%, v ss = 0 v, v a = v dd , v b = 0 v, ?40c < t a < +85c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r- dnl r wb , v a = nc, m onotonic ?1 1/2 +1.8 lsb resistor integral nonlinearity 2 r- inl r wb ,v a = nc ?0.2 +0.2 lsb nominal resistor tolerance r ab /r ab d = 0x3ff ?40 +20 % resistance temperature coeff i cient ( r wb /r wb )/t 10 6 600 ppm/c wiper resistance r w i w = 100 a, v dd = 5.5 v, c ode = half scale 15 100 ? i w = 100 a, v dd = 3 v, c ode = half scale 50 ? dc characteristics potentiometer divider mode resolut ion n 10 bits differential nonlinearity 3 dnl monotonic, t a = 25c ?1 1/2 +1 lsb monotonic, t a = ?40c or +85c ?1 +1.25 lsb integral nonlinearity 3 inl ?0.4 +0.4 lsb voltage divider temperature coeff i cient ( v w /v w )/t 10 6 code = half scale 15 ppm/c full - scale error v wfse code = full scale ?3 0 % fs zero - scale error v wzse code = zero scale 0 1.5 % fs resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance a, b 5 c a, b f = 1 mhz , measured to gnd, code = half - scale 50 pf capacitance w 5 c w f = 1 mhz, measured to gnd, c ode = half - scale 50 pf common - mode leakage cu r rent 5 , 6 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v input logic high v ih with respect to gnd, v dd = 3 v 2.1 v input logic low v il with respect to gnd, v dd = 3 v 0.6 v input logic high v ih with respect to gnd, v dd = +2.5 v, v ss = ?2.5 v 2.0 v input logic low v il with respect to gnd, v dd = +2.5 v, v ss = ?2.5 v 0.5 v output logic high (sdo, rdy) v oh r pull - up = 2.2 k? to 5 v (see figu re 26 ) 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v (see figure 26 ) 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4 pf output current 5 i o1 , i o2 v dd = 5 v, v ss = 0 v, t a = 25c 50 ma v dd = 2.5 v, v ss = 0 v, t a = 25c 7 ma
ad5231 data sheet rev. d | page 4 of 28 parameter symbol conditions min typ 1 max unit power supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd /v ss 2.25 2.75 v positive supply curre nt i dd v ih = v dd or v il = gnd 2.7 10 a negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = ?2.5 v 0.5 10 a eemem store mode current i dd (store) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 40 ma i ss (store) v dd = +2.5 v, v ss = ? 2.5 v ?40 ma eemem restore mode current 7 i dd (restore) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 0.3 3 9 ma i ss (restore) v dd = +2.5 v, v ss = ? 2.5 v ?0.3 ?3 ?9 ma power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensi tivity 5 p ss v dd = 5 v 10% 0.002 0.01 %/% dynamic characteristics 5 , 9 bandwidth bw ?3 db, r ab = 10 k?/50 k?/ 100 k? 370/85/44 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.045 % v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 50 k?, 100 k? 0.022 % v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code 0x000 to 0x200 for r ab = 10 k?/50 k?/100 k? 1.2/3.7/7 s resistor noise vol tage e n_wb r wb = 5 k?, f = 1 khz 9 nv/ hz 1 typical values represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r- inl ) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper pos i tions. r - dnl measures the relative step change from ideal between successive tap positions. i w ~ 50 a @ v dd = 2.7 v and i w ~ 400 a @ v dd = 5 v for the r ab = 10 k? version, i w ~ 50 a for the r ab = 50 k? , and i w ~ 25 a for the r ab = 100 k? version (see figure 26). 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = v ss . dnl spec i fication limits of ?1 lsb minimum are guaranteed monotonic operating condition (see figure 27). 4 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. dual -s upply operation enables ground - referenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common - mode leakage current is a measure of the dc leakage from any terminal b C w to a common - mode bias level of v dd /2. 7 eemem restore mode current is not continuous. current consumed while eemem locations are read and transferred to the rdac register (see figure 23 ). to minimize power dissipation, a nop instruction 0 (0x0) should be issued immediately a fter instruction 1 (0x1). 8 p diss is calculated from (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = +2.5 v and v ss = ?2.5 v.
data sheet ad5231 rev. d | page 5 of 28 timing characteristics10 k, 50 k, 100 k versions v dd = 3 v to 5.5 v, v ss = 0 v, and ?40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit interface timing characteristics 2, 3 clock cycle time (t cyc ) t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1 t cyc input clock pulse width t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 4 t 10 r p = 2.2 k, c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k, c l < 20 pf 0 ns cs high pulse width 5 t 12 10 ns cs high to cs high 5 t 13 4 t cyc rdy rise to cs fall t 14 0 ns cs rise to rdy fall time t 15 0.1 0.15 ms store/read eemem time 6 t 16 applies to instructions 0x 2, 0x3, and 0x9 25 ms power-on eemem restore time t eemem1 r ab = 10 k 140 s dynamic eemem restore time t eemem2 r ab = 10 k 140 s wp high or low to cs fall time t wp 40 ns cs rise to clock rise/fall setup t 17 10 ns preset pulse width (asynchronous) t prw not shown in timing diagram 50 ns preset response time to wiper setting t presp pr pulsed low to refresh wiper positions 70 s flash/ee memory reliability endurance 7 100 kcycles data retention 8 100 years 1 typical values represent av erage readings at 25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see timing diagrams (figure 3 and figure 4) for location of measured values. all in put control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switchin g characteristics are measured using both v dd = 3 v and v dd = 35 v. 4 propagation delay depends on the value of v dd , r pull-up , and c l . 5 valid for commands that do no t activate the rdy pin. 6 rdy pin low only for instructions 2, 3, 8, 9, 10, and the pr hardware pulse: cmd_2, 3 ~ 20 ms; cmd_8 ~ 1 ms; cmd_9, 10 ~ 0.12 ms. device operation at t a = ?40c and v dd < 3 v extends the eemem store time to 35 ms. 7 endurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ?40c, + 25c, and +85c; typical endurance at +25 c is 700,000 cycles. 8 retention lifetime equivalent at junction temperature (t j ) = 55c per jedec standard 22, method a117. retention lifetime base d on an activation energy of 0.6 ev derates with junction temp erature, as shown in figure 45 in the flash/eemem reliability section.
ad5231 data sheet rev. d | page 6 of 28 timing diagrams clk cpol = 1 b24* b23?msb b0?lsb b23?msb high or low high or low b23 b0 b0?lsb rdy cpha = 1 * not defined, but normally lsb of character previously transmitted. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. sdo sdi cs t 2 t 1 t 5 t 4 t 7 t 6 t 10 t 8 t 14 t 11 t 9 t 12 t 3 t 13 t 17 t 15 t 16 02739-003 figure 3. cpha = 1 timing diagram clk cpol = 0 b23?msb out b0?lsb sdo b23?msb in b23 b0 high or low high or low b0?lsb sdi rdy cpha = 0 * not defined, but normally msb of character previously received. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. * cs t 2 t 1 t 4 t 5 t 7 t 6 t 10 t 8 t 14 t 11 t 9 t 12 t 3 t 13 t 17 t 15 t 16 02739-004 figure 4. cpha = 0 timing diagram
data sheet ad5231 rev. d | page 7 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameters ratings v dd to gnd C 0. 3 v, +7 v v ss to gnd +0.3 v, ? 7 v v dd to v ss 7 v v a , v b , v w to gnd v ss ? 0.3 v, v dd + 0.3 v a C b, a C w, b C w intermittent 1 20 ma continuous 2 ma digital input and output voltage to gnd ? 0.3 v, v dd + 0.3 v operating temperature range 2 ? 40c to +85 c maximum junction temperature (t j max) 150c storage temperature ? 65c to +150c reflow soldering peak temperature 2 60c time at peak temperature 20 sec to 40 sec thermal resistance junction -to - ambient ( ja ) ,tssop -16 150c/w junction -to - case ( jc ) , tssop -16 28c/w package power dissipation (t j max ? t a )/ ja 1 maximum terminal cu rrent is bounded by the maximum current ha n dling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resi s tance. 2 includes programming of nonvolatile memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any othe r conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5231 data sheet rev. d | page 8 of 28 pin configuration an d function des criptions 16 15 14 13 12 11 10 9 rdy v dd a w top view (not to scale) ad5231 1 2 3 4 5 6 7 8 clk sdi sdo v ss gnd t o1 b o2 cs pr wp 02739-005 figure 5 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 o1 nonvolatile digital output 1. addr = 0x1, data bit position d0. for example, to store o1 high, the data bit format is 0x310001. 2 clk serial input register clock pin. shifts in one bit at a time on positive clock edges. 3 sdi serial data input pin. shifts in one bit at a time on positive clock clk edges. msb loaded first. 4 sdo serial data outpu t pin. serves readback and daisy - chain functions. command 9 and command 10 activate the sdo output for the readback function, delayed by 24 or 25 clock pulses, depen d ing on the clock polarity before and after the data - word (see fi gure 3 , figure 4 , and table 7 ). in other commands, the sdo shifts out the previously loaded sdi bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see figure 3 and figure 4 ). this previously shifted - out sdi can be used for daisy - chaining multiple devices. whenever sdo is used, a pull - up resistor in the range of 1 k ? to 10 k? is needed. 5 gnd ground pin. logic ground r eference. 6 v ss negative supply. connect to 0 v for single - supply applications. if v ss is used in dual - supply applications, it must be able to sink 40 ma for 25 ms when storing data to eemem. 7 t res erved for factory testing. connect to v dd or v ss . 8 b terminal b of rdac. 9 w wiper terminal of rdac. addr (rdac) = 0x0. 10 a terminal a of rdac. 11 v dd positive power supply pin. 12 wp optional write protect pin. when active low, wp prevents any changes to the present contents, except pr and instruction 1 and instruction 8 and refreshes the rdac register from eemem. execute a nop instruction before returning to wp high. tie wp to v dd , if not used. 13 pr optional hardware override preset pin. refreshes the scratchpad register with current contents of the eemem register. factory default loads midscale 512 10 until eemem is loaded with a new value by the user. pr is activated at the logic high transition. tie pr to v dd , if not used. 14 cs serial register chip select active low. serial register operation takes place when cs ret urns to logic high. 15 rdy ready. active - high open- drain output. identifies completion of instructions 2, 3, 8, 9, 10, and pr . 16 o2 nonvolatile digital output 2. addr = 0x1, data bit position d1. for example, to store o2 high, the data bit format is 0x310002.
data sheet ad5231 rev. d | page 9 of 28 typical performance characteristics code (decimal) 0 inl error (lsb) 1.5 0 ?1.0 1.0 0.5 256 512 768 1024 ?0.5 128 384 640 896 t a = +85c t a = +25c t a = ?40c 02739-006 figure 6 . inl vs. code, t a = ? 40c, +25c, +85c overlay, r ab = 10 k ? code (decimal) dnl error (lsb) 0 ?2.0 2.0 1.0 ?1.0 0 256 512 768 1024 128 384 640 896 ?0.5 1.5 0.5 ?1.5 v dd = 5v, v ss = 0v t a = +85c t a = +25c t a = ?40c 02739-007 figure 7 . dnl vs. code, t a = ? 40c, +25c, +85c overlay, r ab = 10 k ? code (decimal) r-in l (lsb) 0 ?1.0 1.0 0.5 ?0.5 0 256 512 768 1024 128 384 640 896 t a = +85c t a = +25c t a = ?40c v dd = 5v, v ss = 0v 02739-008 figure 8. r - inl vs. code, t a = ? 40c, +25c, +85c overlay, r ab = 10 k ? code (decimal) 0 128 256 384 512 640 768 896 1024 2.0 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 r-dnl (lsb) v dd = 5v, v ss = 0v t a = +85c t a = +25c t a = ?40c 02739-009 figure 9. r - dnl vs. code, t a = ? 40c, +25c, +85c overlay, r ab = 10 k ? code (decimal) rheos ta t mode tempco (ppm/c) 3000 0 256 512 768 1024 128 384 640 896 2500 2000 1500 1000 500 0 v dd = 5.5v, v ss = 0v t a = ?40c to +85c 02739-010 figure 10 . ( ? r wb /r wb )/ ?t 10 6 code (decimal) potentiometer mode tempco (ppm/c) 100 0 256 512 768 1024 128 384 640 896 80 60 40 20 0 ?20 v dd = 5.5v, v ss = 0v t a = ?40c to +85c v b = 0v v a = 2.00v 02739-011 figure 11 . ( ? v w /v w )/ ?t 10 6
ad5231 data sheet rev. d | page 10 of 28 code (decimal) r w (?) 60 0 256 512 768 1024 128 384 640 896 50 40 30 20 10 0 v dd = 2.7v, v ss = 0v t a = 25c 02739-012 figure 12 . wiper on res istance vs. code temperature (c) current (a) 4 ?40 0 40 80 ?20 20 60 100 3 2 1 0 ?1 i dd @ v dd /v ss = 5v/0v i ss @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 2.7v/0v i ss @ v dd /v ss = 2.7v/0v 02739-013 figure 13 . i dd vs. temperature, r ab = 10 k ? clock frequenc y (mhz) i dd (ma) 0.25 0 2 4 6 8 10 12 0.20 0.15 0.10 0.05 0 v dd = 5v v ss = 0v midscale zero-scale full-scale 02739-014 figure 14 . i dd vs. clock frequency, r ab = 10 k ? frequency (hz) 2 0 ?16 1k 10k gain (db) ?2 ?4 ?12 ?6 ?8 ?10 ?14 100k 1m f ?3db = 37khz, r ab = 10k? f ?3db = 44khz, r ab = 100k? f ?3db = 85khz, r ab = 50k? v a = 1mv rms v dd /v ss = 2.5v d = midscale 02739-015 figure 15 . ?3 db b andwidth vs. resistance ( figure 32 ) frequency (khz) 0.12 0.01 thd + noise (%) 0.10 0.08 0.04 0 0.1 1 10 100 0.06 0.02 v dd /v ss = 2.5v v a = 1v rms r ab = 10k? 50k? 100k? 02739-016 figure 16 . total harmonic distortion vs. frequency frequenc y (hz) 0 ?50 1k gain (db) ?25 100k 10k ?5 ?30 ?35 ?40 ?45 ?20 ?10 ?15 1m 10m code = 0x200 0x100 0x80 0x40 0x20 0x10 0x01 0x02 0x04 0x08 02739-017 figure 17 . gain vs. frequency vs. code, r ab = 10 k ? ( figure 32 )
data sheet ad5231 rev. d | page 11 of 28 frequenc y (hz) 0 ?50 1k gain (db) 100k 10k ?30 ?40 ?20 ?10 1m 0x04 0x01 ?60 0x02 code = 0x200 0x100 0x80 0x40 0x20 0x10 0x08 02739-018 figure 18 . gain vs. frequency vs. code, r ab = 50 k ? ( figure 32 ) frequency (hz) 0 ?50 1k gain (db) 100k 10k ?30 ?40 ?20 ?10 1m 0x04 0x01 ?60 0x02 code = 0x200 0x100 0x80 0x40 0x20 0x10 0x08 02739-019 figure 19 . gain vs. frequency vs. code, r ab = 100 k ? ( figure 32 ) frequency ( hz) psrr (?db) 80 100 10k 1m 1k 100k 10m 70 50 30 20 0 60 40 10 v dd = 5.0v 100mv ac v ss = 0v, v a = 5v, v b = 0v measured at v w with code = 0x200 r ab = 100k? r ab = 50k? r ab = 10k? 02739-020 figure 20 . psrr vs. f requency 100s/div v dd = 5v v a = 2.25v v b = 0v v a v w 0.5v/div expected value midscale 100 90 10 0% 02739-021 figure 21 . power - on reset, v a = 2.25 v, v b = 0 v, code = 1010101010 b time (s) v out (v) 2.55 0 10 20 5 15 25 2.53 2.51 2.49 2.47 2.45 v dd /v ss = 5v/0v code = 0x200 to 0x1ff r ab = 10k? r ab = 50k? r ab = 100k? 02739-022 figure 22 . midscale glitch energy, code 0x200 to 0x1ff 4ms/div 5v/div 5v/div 5v/div cs clk sdi i dd 20ma/div 02739-023 figure 23 . i dd vs. time when storing data to eemem
ad5231 data sheet rev. d | page 12 of 28 4ms/div 5v/div 5v/div 5v/div cs clk sdi * supply current returns to minimum power consumption if instruction 0 (nop) is executed immediately after instruction 1 (read eemem). i dd * 2ma/div 02739-024 figure 24 . i dd vs. time when restoring data from eemem code (decimal) 100 1 0.01 1024 theoretical?i wb_max (ma) 0.1 10 896 768 640 512 384 128 256 0 v a = v b = open t a = 25c r ab = 10k? r ab = 50k? r ab = 100k? 02739-025 figure 25 . i wb_max vs. code
data sheet ad5231 rev. d | page 13 of 28 test circuits figure 26 to figure 35 define the test conditions used in the specifications. a w b nc i w dut v ms nc = no connect 02739-026 figure 26 . resistor position nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n 02739-027 figure 27 . potentiometer divider nonlinearity error (inl, dnl) a w b dut i w v ms1 v ms2 v w r w = [v ms1 ? v ms2 ]/i w 02739-028 figure 28 . wiper resistance a w b v ms v a v dd v+ v+ = v dd 10% psrr (db) = 20 log v ms v dd pss (%/%) = v ms % v dd % 02739-029 figure 29 . power supply sensitivity (pss, psrr) offset bias offset gnd a b dut w 5v v in v out op279 02739-030 figure 30 . inverting gain offset bias offset gnd a b dut w 5v v in v out op279 02739-031 figure 31 . noninverting gain offset gnd a b dut w +15v v out v in op42 ?15v +2.5v 02739-032 figure 32 . gain vs. frequency + ? dut nc code = 0x000 0.1v v bias r sw = 0.1v i sw i sw w b a nc = no connect 02739-033 figure 33 . incremental on resistance i cm v cm w b v dd dut nc nc gnd v ss a nc = no connect 02739-034 figure 34 . common - mode leakage current 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 02739-057 figure 35 . load circuit for measuring v oh and v ol (the diode bridge test circuit is equivalent to the application circuit with r pull - up of 2.2 k ?)
ad5231 data sheet rev. d | page 14 of 28 theory of operation the ad5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to v dd ? v ss < 5.5 v. the dig i tal potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct positio n. the scratchpad register can be programmed with any position value using the standard spi serial interface mode by loading the complete representative data - word. once a desirable position is found, this value can be stored in an eemem register. thereafte r, the wiper position is always restored to that position for subsequent power - up. the storing of eemem data takes approximately 25 ms; during this time, the shift register is locked, preventing any changes from taking place. the rdy pin pulses low to ind icate the co m pletion of this eemem storage. the following instructions facilitate the users programming needs (see table 7 for details): 0. do nothing. 1. restore eemem content to rdac. 2. store rdac setting to eemem. 3. store rdac setting or user data to eemem. 4. decrement 6 db. 5. decrement 6 db. 6. decrement one step. 7. decrement one step. 8. reset eemem content to rdac. 9. read eemem content from sdo. 10. read rdac wiper setting from sdo. 11. write data to rdac. 12. increment 6 db. 13. increment 6 db. 14. increment one ste p. 15. increment one step. scratchpad and eemem programming the scratchpad rdac register directly controls the position of the digital potentio meter wiper. for example, when the scratc h pad register is loaded with all zeros, the wiper is connected to terminal b of the variable resistor. the scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the eemem registers have a program erase /write cycle limitation (see the flash/eemem reliabil ity section). basic operation the basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loa d ing the serial data input register with instruction 11 (0xb), a d dress 0, and the desired wiper posit ion data. when the proper wiper position is determined, the user can load the serial data input register with instruction 2 (0x2), which stores the wiper position data in the eemem register. after 25 ms, the wiper position is permanently stored in the nonv olatile me m or y. table 5 provides a programming example listing the sequence of serial data input (sdi) words with the serial data output appea r ing at the sdo pin in hexadecimal format. table 5 . set and sto re rdac data to eemem register sdi sdo action 0xb00100 0xxxxxxx writes data 0x100 to the rdac regi s ter, wiper w moves to 1/4 full - scale position. 0x20xxxx 0xb00100 stores rdac register content into the eemem register. at system power - on, the scratchp ad register is automatically refreshed with the value previously stored in the eemem regi s ter. the factory - preset eemem value is midscale, but it can be changed by the user thereafter. during operation, the scratchpad (rdac) register can be r e freshed wi th the eemem register data with instruction 1 (0x1) or instruction 8 (0x8). the rdac register can also be refreshed with the eemem register data under hardware control by pul s ing the pr pin. the pr pulse first sets the wiper at midscale when brought to logic zero, and then, on the pos i tive transition to logic high, it reloads the rdac wiper register with the co n tents of eemem. many additional advanced programming commands are avai l able to simplify the variable resistor adjustment process (see table 7 ). for example, the wiper position can be changed one step at a time using the increment/decrement instruction or by 6 db with the shift left/right instruction. once an increment, decrement, or shift instruction has been loaded into the shift regi s ter, subsequent cs strobes can repeat this command. a serial data output sdo pin is available for daisy - chaining and for readout of the internal register contents. eemem protection the wri te protect ( wp ) pin disables any changes to the scratc h pad register contents, except for the eemem setting, which can still be restored using instruction 1, instruction 8, and the pr pulse. therefore, wp can be used to provide a hardware e e mem protection feature. to disable wp , it is recommended to execute a nop instruction before returning wp to logic high.
data sheet ad5231 rev. d | page 15 of 28 digital input/output configuration all digital inputs are esd - protected, high input impedance that can be driven directly from most digital sources. active at logic low, pr and wp must be tied to v dd i f they are not used. no internal pull - up resistors are present on any digital in put pins. the sdo and rdy pins are open - drain digital outputs that need pull - up resistors only if these functions are used. a resi s tor value in the range of 1 k? to 10 k? is a proper choice that ba l ances the dissipation and switching speed. the equivalent serial data input and output logic is shown in figure 36 . the open - drain output sdo is disabled whenever chip - select cs is in logic high. esd protection of the digital inputs is shown in figure 37 and figure 38. counter serial register clk sdi 5v r pull-up sdo gnd pr wp ad5231 cs command processor and address decode valid command 02739-035 figure 36 . equivalent digital input - output logic logic pins v dd gnd input 300? 02739-036 figure 37 . equivalent esd digital input protection gnd wp v dd input 300? 02739-037 figure 38 . equivalent wp input protection serial data interfac e the ad5231 contains a 4 - wire spi - compatible digital interface (sdi, sdo, cs , and clk). it uses a 24 - bit serial data - word loaded msb first. the format of the spi - compatible word i s shown in table 6 . the chip - select cs pin must be held low until the complete data - word is loaded into the sdi pin. when cs returns high, the serial data - word is decoded according to the instru ctions in table 7 . the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into the decoded register. the ad5231 has an internal counter that counts a multiple of 24 bits (a frame) for proper operation. for example, ad5231 works with a 48 - bit word, but it cannot work properly with a 23- bit or 25 - bit word. in addition, ad5231 has a subtle feature that, i f cs is pulsed without clk and sdi, the part repeats the pr e vious command (except during power - up). as a result, care must be taken to ensure that no excessive noise exists in the clk or cs line that might alter the effe ctive number of bits (enob) pattern. also, to prevent data from mislocking (due to noise, for example), the counter resets if the count is not a mu l tiple of four when cs goes high. the spi interface can be used in two slave modes: cpha = 1, cpol = 1 and cpha = 0, cpol = 0. cpha and cpol refer to the control bits that dictate spi timing in the following micr o converters ? and microprocessors: aduc812/aduc824, m68hc11, and mc68hc16r1/916r1. daisy - chain operation the serial data output pin (sd o) serves two purposes. it can be used to read the contents of the wiper setting and eemem va l ues using instruction 10 and instruction 9, respectively. the remaining instructions (0 to 8, 11 to 15) are valid for daisy - chaining multiple devices in simultane ous operations. daisy - chaining minimizes the number of port pins required from the contro l ling ic ( see figure 39 ). the sdo pin contains an open - drain n - ch fet that requires a pull - up resistor if this function is used. as shown i n figure 39 , users need to tie the sdo pin of one pac k age to the sdi pin of the next package. users might need to increase the clock period, because the pull - up resistor and the capacitive loading at the sdo to sdi interface mig ht require additional time delay between sub - s e quent packages. when two ad5231s are daisy - chained, 48 bits of data are required. the first 24 bits go to u2 and the se c ond 24 bits go to u1. the cs should be kept low until all 48 bits are clocked into their respective serial registers. the cs is then pulled high to complete the operation. sdi sdo clk r p 2k? c sdi sdo clk u1 u2 ad5231 ad5231 cs cs +v 02739-038 figure 39 . daisy - chain configuration using sdo
ad5231 data sheet rev. d | page 16 of 28 terminal voltage ope ration range the ad5231s positive v dd an d negative v ss power supplies define the boundary conditions for proper 3 - terminal digital potentiometer operation. supply signals present on the a, b, and w terminals that exceed v dd or v ss are clamped by the internal forward - biased diodes (see figure 40). the ground pin of the ad5231 device is primarily used as a digital ground reference, which needs to be tied to th e common ground of the pcb . the digital input control signals to the ad5231 must be referenced to the device ground pin (gnd) and satisfy the logic level defined in the specifications section. an internal level - shift circuit ensures that the common - mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital inp ut level. v ss v dd a w b 02739-039 figure 40 . maximum terminal voltages set by v dd and v ss power - up sequence because there are diodes to limit the voltage compliance at the a, b, and w t erminals ( figure 40 ), it is important to power v dd /v ss first before a pplying any voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward - biased such that v dd /v ss are powered unintentionally and might affect the rest of the users circuit. the ideal power - up sequence is gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd /v ss . regardless of the power - up sequence and the ramp rates of the power supplies, once v dd /v ss are po wered, the power - on preset remains effective, which restores the eemem value to the rdac register. latched digital outp uts a pair of digital outputs, o1 and o2, is available on the ad5231. these outputs provide a nonvolatile logic 0 or logic 1 setting. o1 and o2 are standard cmos logic outputs, shown in figure 41 . these outputs are ideal to replace the functions often provided by dip switches. in addition, they can be used to drive other standard cmos logic - controlled parts that ne ed an occ a sional setting change. pin o1 and pin o2 default to logic 1, and they can drive up to 50 ma of load at 5 v/25c. v dd gnd outputs o1 and o2 pins 02739-040 figure 41 . logic outputs o1 and o2
data sheet ad5231 rev. d | page 17 of 28 in table 6 , command bits are c0 to c3, addr ess bits are a3 to a0, data bit d0 to data bit d9 are applicable to rdac, and d0 to d15 are applic a ble to eemem. table 6 . ad5231 24 - bit serial data - word msb command byte 0 data byte 1 data byte 0 lsb rdac c3 c2 c1 c0 0 0 0 0 x x x x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eemem c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command instruction codes are defined in table 7 . table 7 . command/operation tru th table 1, 2, 3 instruction number command byte 0 data byte 1 data byte 0 operation b23 b16 b15 b8 b7 b0 c3 c2 c1 c0 a3 a2 a1 a0 x d9 d8 d7 d0 0 0 0 0 0 x x x x x x x x x nop: do nothing. see table 15 . 1 0 0 0 1 0 0 0 0 x x x x x restore eemem(0) contents to rdac register. this command leaves the d e vice in the read program power state. to return the part to the idle state, perform nop instruction 0. see table 15 . 2 0 0 1 0 0 0 0 0 x x x x x store wiper setting: store rdac setting to eemem(0). see table 14 . 3 4 0 0 1 1 a3 a2 a1 a0 d15 d8 d7 d0 store contents of data bytes 0 and 1 (total 16 bits) to eemem (addr 1to addr 15). see table 17 . 4 5 0 1 0 0 0 0 0 0 x x x x x decrement rdac by 6 db. 5 5 0 1 0 1 x x x x x x x x x same as instruction 4. 6 5 0 1 1 0 0 0 0 0 x x x x x decrement rdac by 1 position. 7 5 0 1 1 1 x x x x x x x x x same as instruction 6. 8 1 0 0 0 x x x x x x x x x reset: restor e rdac with eemem (0) value. 9 1 0 0 1 a3 a2 a1 a0 x x x x x read eemem (addr 0 to addr 15) from sdo output in the next frame. see table 18 . 10 1 0 1 0 0 0 0 0 x x x x x read rdac wiper setting from sdo o utput in the next frame. see table 19 . 11 1 0 1 1 0 0 0 0 x d9 d8 d7 d0 write contents of data bytes 0 and 1 (total 10 bits) to rdac. see table 13 . 12 5 1 1 0 0 0 0 0 0 x x x x x increment rdac by 6 db. see table 16 . 13 5 1 1 0 1 x x x x x x x x x same as instruction 12. 14 5 1 1 1 0 0 0 0 0 x x x x x increment rdac by 1 position. see table 14 . 15 5 1 1 1 1 x x x x x x x x x same as instruction 14. 1 the sdo output shifts out the last 24 bits of data clocked into the serial register for daisy - cha in operation. exception: for any instruction following instruction 9 or instruction 10, the selected internal register data is present in d ata byte 0 and data byte 1. the instruction following 9 and 10 must also be a full 24 - bit data - word to completely clock out the contents of the serial register. 2 the rdac register is a volatile scratch pad register that is refreshed at power - on from the corresponding nonvolatile eemem register. 3 execution of these operations takes place when the cs str obe returns to logic high. 4 instruction 3 write s two data bytes (16 bits of data) to eemem. in the case of 0 addresses, only the last 10 bits are valid for wiper position setting . 5 the increment, decrement, and shift instructions ignore the contents of t he shift register d ata byte 0 and data byte 1.
ad5231 data sheet rev. d | page 18 of 28 advanced control mod es the ad5231 digital potentiometer includes a set of user programming features to address the wide number of applic a tions for these universal adjustment devices. key programming features include: ? scratchpad progr amming to any desirable values ? nonvolatile memory storage of the scratchpad rdac regi s ter value in the eemem register ? increment and decrement instructions for the rdac wiper register ? left and right bit shift of the rdac wiper register to achieve 6 db leve l changes ? 28 extra bytes of user - addressable nonvolatile memory linear increment and decrement instructions the increment and decrement instructions (14, 15, 6, and 7) are useful for linear step - adjustment applications. these commands simplify microcontrol ler software coding by allowing the co n troller to send just an increment or decrement command to the device. for an increment command, executing instruction 14 with the proper address automatically moves the wiper to the next resistance segment position. instruction 15 performs the same fun c tion, except that the address does not need to be specified. logarithmic taper mode adjustment four programming instructions produce logarithmic taper increment and decrement of the wiper. these settings are act i vated by the 6 db increment and 6 db decrement instructions (12, 13, 4, and 5). for example, starting at zero scale, executing the increment instruction 12 eleven times moves the wiper in 6 db per step from 0% to full scale, r ab . the 6 db increment i n struction d oubles the value of the rdac register contents each time the command is executed. when the wiper position is near the maximum setting, the last 6 db increment instruction causes the wiper to go to the full - scale 1023 code position. fu r ther 6 db per increme nt instructions do not change the wiper position beyond its full scale. the 6 db step increments and 6 db step decrements are achieved by shifting the bit internally to the left or right, respe c tively. the following information explains the nonideal 6 db step adjustment under certain conditions. table 8 illu s trates the operation of the shifting function on the rdac register data bits. each table row represents a successive shift oper a tion. note that the left - shift 12 and 13 instru ctions were mod i fied such that, if the data in the rdac register is equal to zero and the data is shifted left, the rdac register is then set to code 1. similarly, if the data in the rdac register is greater than or equal to midscale and the data is shifte d left, then the data in the rdac register is automatically set to full scale. this makes the left - shift function as ideal a logarithmic adjus t ment as po s sible. the right - shift 4 and 5 instructions are ideal only if the lsb is 0 (ideal logarithmic = no err or). if the lsb is 1, the right - shift function generates a linear half - lsb error, which translates to a nu m ber - of - bits dependent logarithmic error, as shown in figure 42 . the plot shows the error of the odd numbers of bits for t he ad5231. table 8 . detail left - shift and right - shift functions for 6 db step increment and decrement left - shift (+6 db/s tep) left - shift right - shift right - shift ( C 6 db/s tep) 00 0000 0000 11 1111 1111 00 0000 0001 01 1111 11 11 00 0000 0010 00 1111 1111 00 0000 0100 00 0111 1111 00 0000 1000 00 0011 1111 00 0001 0000 00 0001 1111 00 0010 0000 00 0000 1111 00 0100 0000 00 0000 0111 00 1000 0000 00 0000 0011 01 0000 0000 00 0000 0001 10 0000 0000 00 00 00 0000 11 1111 1111 00 0000 0000 11 1111 1111 00 0000 0000 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right - shift 4 and 5 command execution contains an error only for od d numbers of bits. even numbers of bits are ideal. the graph in figure 42 shows plots of log_error [20 log 10 (e r ror/code)] for the ad5231. for example, code 3 log_error = 20 log 10 (0.5/3) = ?15.56 db, which is the worst case. the plot of log_error is more significant at the lower codes. code (from 1 to 1023 by 2.0 10 3 ) 0 (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 ?40 ?20 ?60 ?80 02739-041 figure 42 . plot of log_ error conformance for odd numbers of bits only (even numbers of bits are ideal)
data sheet ad5231 rev. d | page 19 of 28 using additional internal nonvolatile eemem the ad5231 contains additional user eemem registers for storing any 16 - bit data such as memory data for other comp o - nents, look - up tables, or system identification information. table 9 provides an addre ss map of the internal storage regi s ters shown in the functional block diagram as eemem1, e e mem2, and 28 bytes (14 addresses 2 bytes each) of user eemem. table 9 . eemem address map address eemem for 0000 rdac 1, 2 0001 o1 and o2 3 0010 user1 4 0011 user2 1110 user13 1111 user14 1 rdac data stored in eemem location is transferred to the rdac regi s ter at power - on, or when instruction 1, instruction 8, or pr are ex e cuted. 2 execution of instruction 1 leav es the device in the read mode power co n sumption state. after the last instruction 1 is executed, the user should perform a nop, i n struction 0 to return the device to the low power idling state. 3 o1 and o2 data stored in eemem locations is transferred to the correspon d ing digital register at power - on, or when instruction 1 and instruction 8 are executed. 4 userx are internal nonvolatile eemem registers available to store 16 - bit information using instruction 3 and restore the contents using i n struction 9. r dac structure the patent - pending rdac contains multiple strings of equal resistor segments with an array of analog switches that act as the wiper connection. the number of positions is the resolution of the device. the ad5231 has 1024 connection points, al lo w ing it to provide better than 0.1% settability resolution. figure 43 shows an equivalent structure of the connections among the three terminals of the rdac. the sw a and sw b are always on, while the switches sw(0) to sw(2 n ?1) ar e on one at a time, depending on the resistance position decoded from the data bits. because the switch is not ideal, there is a 15 ? wiper resi s tance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage or th e higher the temperature, the higher the resulting wiper resistance. users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed. sw(1) sw(0) sw b b sw a sw(2 n ?1) sw(2 n ?2) a w r s r s r s r s = r ab /2 n digital circuitry omitted for clarity rdac wiper register and decoder 02739-042 figure 43 . equivalent rdac structure (patent p ending) table 10 . nominal individual segment resistor (r s ) device resol u tion 10 k? ve r sion 50 k? ve r sion 100 k? version 10- bit 9.8 ? 48.8 ? 97.6 ? programming the vari able resistor rheostat operation the nominal resistan ce of the rdac between terminal a and terminal b, r ab , is available with 10 k?, 50 k?, and 100 k? with 1024 posit ions (10 - bit resolution). the final digit(s) of the part number determine the nominal resistance value, for example, 10 k? = 10; 50 k? = 50; 100 k? = c. the 10 - bit data - word in the rdac latch is decoded to select one of the 1024 possible settings. the foll owing discussion d e scribes the calculation of resistance r wb at different codes of a 10 k? part. for v dd = 5 v, the wipers first connection starts at terminal b for data 0x000. r wb (0) is 15 ? because of the wiper resistance, and because it is independent of the nominal resi s tance. the second connection is the first tap point where r wb (1) becomes 9.7 ? + 15 ? = 24.7 ? for data 0x001. the third co n nection is the next tap point representing r wb (2) = 19.4 ? + 15 ? = 34.4 ? for data 0x002 and so on. each lsb data value i n crease moves the wiper up the resistor ladder until the last tap point is reached at r wb (1023) = 10 , 005 ?. see figure 43 for a simplified diagram of the equivalent rdac circuit. when r wb is used, terminal a can be l eft floating or tied to the wiper.
ad5231 data sheet rev. d | page 20 of 28 code (decimal) 100 75 0 0 1023 256 r wa (d), r wb (d); (% of nominal r ab ) 512 768 50 25 r wb r wa 02739-043 figure 44 . r wa (d) and r wb (d) vs. decimal code the general equation that determines the programmed output resistance between w and b is w ab wb r r d d r + = 1024 ) ( (1) where: d is the decimal equival ent of the data contained in the rdac register. r ab is the nomi nal resistance between terminal a and terminal b . r w is the wiper resistance. for example, the output resistance values in table 11 are set for the given rdac latch codes with v dd = 5 v (applies to r ab = 10 k? digital potentiometers). table 11. r wb (d) at selected codes for r ab = 10 k? d (dec) r wb (d) ( ? ) output state 1023 10,005 full scale 512 50, 015 midscale 1 24.7 1 lsb 0 15 zero scale (wiper contact resistor) note that, in the zero - scale condition, a finite wiper resistance of 15 ? is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible des truction of the internal switches . like the mechanical potentiometer that the rdac replaces, the ad5231 part is totally symmetrical. the resistance between wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . figure 44 shows the symmetr i cal programmability of the various terminal connections. when r wa is used, terminal b can be left floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is w ab wb r r d d r + ? = 1024 1024 ) ( (2) for example, the output resistance values in table 12 are set for the rdac latch codes with v dd = 5 v (applies to r ab = 10 k? digital potentiometers). table 12. r wa (d) at selected codes for r ab = 10 k? d (dec) r wa (d) (?) output state 1023 24.7 full scale 512 5015 midscale 1 10005 1 lsb 0 10,015 zero scale the typical distribution of r ab from device to device matches tightly when they are processed in the same batch. when devices are processed at a different time, device - to - device matc h ing becomes process - lot dependent and exhibits a ?40% to +20% variation. the change in r ab with temperature h as a 600 ppm/c temperature coefficient. programming the pote ntiometer d i vider voltage output operation the digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the input voltages applied to te rminal a and terminal b. for example, connecting terminal a to 5 v and terminal b to ground pr o duces an output voltage at the wiper that can be any value from 0 v to 5 v. each lsb of voltage is equal to the voltage applied across terminal s a C b divided by t he 2 n position resolution of the pote n tiometer divider. because ad5231 can also be supplied by dual supplies, the ge n eral equation defining the output voltage at v w with respect to ground for any given input voltages applied to terminal a and terminal b i s b ab w v v d d v + = 1024 ) ( (3) equation 3 assumes that v w is buffered so that the effect of wiper resistance is minimized. operation of the digital potent i ometer in divider mode results in more accurate operation over temperature. here, the output voltage i s dependent on the ratio of the internal resistors and not the absolute value; ther e fore, the drift improves to 15 ppm/c. there is no voltage pola r it y restric tion between terminal a, terminal b, and terminal w as long as the term i nal voltage (v term ) stay s within v ss < v term < v dd .
data sheet ad5231 rev. d | page 21 of 28 programming examples the following programming examples illustrate a typical s e quence of events for various features of the ad5231. see table 7 for the instructions and data - word format. the instru c t ion numbers, addresses, and data appearing at sdi and sdo pins are in hexadecimal format. table 13 . scratchpad programming sdi sdo action 0xb00100 0xxxxxxx writes data 0x100 into rdac register, wip er w moves to 1/4 full - scale pos i tion . table 14 . incrementing rdac followed by storing the wiper setting to eemem sdi sdo action 0xb00100 0xxxxxxx writes data 0x100 into rdac register, wiper w moves to 1/4 full - scale pos i tion. 0xe0xxxx 0xb00100 increments rdac register by one to 0x101. 0xe0xxxx 0xe0xxxx increments rdac register by one to 0x102. continue until desired wiper position is reached. 0x20xxxx 0xxxxxxx stores rdac register data into e e mem(0). optionally tie wp to gnd to protect eemem values. the eemem value for the rdac can be restored by power - on, by strobing the pr pin, or by pr ogramming, as shown in table 15. table 15 . restoring the eemem value to the rd ac register sdi sdo action 0x10xxxx 0xxxxxxx restores the eemem(0) value to the rdac register. 0x00xxxx 0x10xxxx nop. recommended step to minimize power consumption. table 16 . using left - shift by one to increment 6 db step sdi sd o action 0xc0xxxx 0xxxxxxx moves the wiper to double the pr e sent data contained in the rdac register. table 17 . storing additional user data in eemem sdi sdo action 0x32aaaa 0xxxxxxx stores data 0xaaaa in the extra eemem locatio n user1. (a l lowable to address in 14 locations with a max i mum of 16 bits of data.) 0x335555 0x32aaaa stores data 0x5555 in the extra eemem location user2. (a l lowable to address in 14 locations with a max i mum of 16 bits of data.) table 18. re a ding back data from memory locations sdi sdo action 0x92xxxx 0xxxxxxx prepares data read from e e mem(2) location. 0x00xxxx 0x92aaaa nop instruction 0 sends a 24 - bit word out of sdo, where the last 16 bits contain the contents in the eemem(2) location. the nop command ensures that the device returns to the idle power dissipation state. table 19 . reading back wiper settings sdi sdo action 0xb00200 0xxxxxxx writes rdac to midscale. 0xc0xxxx 0xb00200 doubles rdac from mi dscale to full scale (left - shift instruction). 0xa0xxxx 0xc0xxxx prepares reading wiper setting from rdac register. 0xxxxxxx 0xa003ff reads back full - scale value from sdo.
ad5231 data sheet rev. d | page 22 of 28 flash/eemem reliabil ity the flash/ee memory array on the ad5231 is fully qual i fi ed for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data rete n tion. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four indepen d ent, sequential events. these events are defined as ? initial page erase sequence ? read/verify sequence ? byte program sequence ? second read/verify sequence during reliability qualification, flash/ee memory i s cycled from 0x000 to 0x3ff until a first fail is recorded signifying the endurance limit of the on - chip flash/ee memory. as indicated in the specifications section, the ad5231 flash/ee memory endurance qualification has been carr ied out in accordance with jedec specification a117 over the industrial temperature range of ?40c to +85c. the results allow the specification of a minimum endurance figure over supply and te m perature of 100,000 cycles, with an endurance figure of 700,000 cycles be ing typical of operation at 25c. retention quantifies the ability of the flash/ee memory to r e tain its programmed data over time. again, the ad5231 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specif ic junction temper a ture (t j = 55c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit, described previously, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is reprogrammed. it should also be noted that rete n tion lifetime, based on an activation energy of 0.6 ev, derates with t j , as shown in figur e 45 . for example, the data is retained for 100 years at 55c operation , b ut reduces to 15 years at 85c o p eration. beyond these limits, the part must be reprogrammed so that the data can be restored. 300 250 0 40 retention (years) 200 150 100 50 50 60 70 80 90 100 110 t j junction temperature (c) analog devices typical performance at t j = 55c 02739-044 figure 45 . flash/ee memory data retention
data sheet ad5231 rev. d | page 23 of 28 applications bipolar operation fr om dual su p plies the ad5231 can be operated from dual supplies 2.5 v, which enables control of ground referenced ac signals or bipolar operation. ac signals as high as v dd /v ss can be applied d i rectly acr oss terminal a to terminal b with output taken from terminal w. see figure 46 for a typical circuit connection. 2.5v p-p ad5231 v ss gnd sdi clk ss sclk mosi gnd c 1.25v p-p v dd v dd +2.5v ?2.5v cs d = midscale a w b 02739-045 figure 46 . bipolar operation from dual supplies high voltage operati on the digital potentio meter can be placed directly in the feedback or input path of an op amp for gain control, provided t hat the voltage across terminal s a C b, terminal s w C a, or terminal s w C b does not exceed | 5 v | . when high voltage gain is needed, users should set a fixed gain in an op amp operated at a higher voltage and let the dig i tal potentiometer control the adjustable input. figure 47 shows a simple implementation. r 2r 5v ad5231 a w b 15v v+ v? v o 0v to 15v a1 ? + c c 2.2pf 02739-046 figure 47 . 15 v voltage span control bipolar programmab le gain amplifier there are several ways to achieve bipolar gain. figure 48 shows one versatile implementation. digital potentiometer u1 sets the adjustment range; the wiper voltage v w2 can, therefore, be pr o grammed between v i and ?kv i at a given u2 setting. for linear adjustment, configure a2 as a noninverting amplifier and the transfer function becomes ? ? ? ? ? ? ? + ? ? ? ? ? ? + = ) 1 ( 1024 1 (4) where: k is the ratio of r wb /r wa that is set by u1. d is the decimal equivalent of the input code. v+ v? op2177 ad5231 v+ v? op2177 ad5231 vi a w b ?kvi a b w v dd v o v ss r1 r2 a u2 a2 u1 c c 2.2pf v dd v ss 02739-047 figure 48 . bipolar programmable gain amplifier in the simpler (and much more usual) case where k = 1, a pair of matched resistors can replace u1. equation 4 can be simpl i fied to ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 1024 2 1 2 d r1 r2 v v i o (5) table 20 shows the result of adjusting d with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bip o lar amplifier with linearly programmable gain and 1024 - step res o lution. table 20 . result of bipolar g ain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 ? 1 ? 2 ? 10 256 ? 0.5 ? 1 ? 5 512 0 0 0 768 0.5 1 5 1023 0.992 1.984 9.92 10- bit bipolar dac if the circuit in figure 48 is changed with the input taken from a voltage referenc e and a2 configured as a buffer, a 10 - bit b i polar dac can be realized. compared to the conventional dac, this circuit offers comparable resolution but not the pr e cision because of the wiper resistance effects. degradation of the nonli n earity and temperatu re coefficient is prominent near both ends of the adjustment range. on the other hand, this ci r cuit offers a unique nonvolatile memory feature that in some cases ou t weighs any shortfall in precision. the output of this circuit is ref o v d v ? ? ? ? ? ? ? = 1 1024 2 2 (6)
ad5231 data sheet rev. d | page 24 of 28 v+ v? ad8552 ad5231 v o v+ v? ad8552 ?2.5vref b a w a1 u1 + 2.5vref v out v in trim gnd adr421 +5v ?5v ?5v +5v r r a2 +5v 02739-048 figure 49 . 10 - bit bipolar dac 10- bit unipolar dac figure 50 shows a unipolar 10 - bit dac using ad5231. the buffer is needed to drive various leads. ad5231 v+ v? ad8601 w a1 gnd ad1582 5v 5v u1 3 a b v o 1 2 v out v in 02739-049 figure 50 . 10 - bit unipola r dac programmable voltage source with boosted output for applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 51). ad5231 v+ v? w ad8601 a b v in v out i l 2n7002 r bias signal c c ld u2 02739-058 figure 51 . programmable booster voltage source in this circuit, the inverting input of the op amp forces the v out to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n - ch fet n 1 . n 1 power handling must be adequate to dissipate (v i ? v o ) i l power. this circuit can source a maximum of 100 ma with a 5 v supply. for precision applications, a voltage reference such as adr421 , adr03 , or adr370 can be applied at terminal a of the digital potentiometer. programmable current source a programmable current source can be implemented with the circuit shown in figure 52. v+ v? op1177 u2 v in sleep ref191 gnd v out 3 2 4 6 u1 ad5231 w a b v l i l +5v ?5v +5v + ? ?2.048v to v l 0v to (2.048v + v l ) r s 102? c1 1f r l 100? 02739-051 figure 52 . programmable current source ref191 is a unique low supply, headroom precision reference that can deliver the 20 ma needed at 2.048 v. the load current is simply the volt age across term inal s b C w of the digital pote n tiometer divided by r s : 1024 u u s ref l r d v i (7) the circuit is simple , but be aware that there are two issues. first, dual - supply op amps are ideal because the ground pote n tial of ref191 can swing from ?2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single - supply, the programmable resolution of the system is reduced. second, the voltage compliance at v l is li m ited to 2.5 v or equiva lently a 125 ? load. should higher voltage compliance be needed, users can consider digital potentiom e ters ad5260 , ad5280 , and ad7376 . figure 53 shows an alte r nate circuit for high voltage compliance. to achieve higher current, such as when driving a high power led, the user can replace the ui with an ldo, reduce r s , and add a resistor in series with the digital potentiometers a terminal. this limits the potentiometers current and i n creases the current adjustment resolution.
data sheet ad5231 rev. d | page 25 of 28 programmable bidirec tional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution. if the resistors are matched, the load current is ( ) w l v r2b r1 r2b r2a i + = (8) ?15v op2177 v+ v? +15v + ? c1 10pf r2 n? r1 n? r l ? r2b ? v l r1 n? r2a n? i l op2177 v+ v? +15v + ? ?15v a1 ad5231 a b w +2.5v ?2.5v a2 02739-052 figure 53 . programmable bidirectional current source r2b, in theory, can be made as small as nece ssary to achieve the current needed within the a2 output current - driving cap a bility. in this circuit, op2177 delivers 5 ma in both directions, and the voltage compliance approaches 15 v. it can be shown that t he output impedance is ) ( ) ( r2b r2a r1' r1r2' r2a r1 r2b r1' z o + ? + = (9) z o can be infinite if resistors r1 and r2 match precisely with r1 and r2a + r2b, respectively. on the other hand, z o can be negative if the resistors are not matched. as a result , c1, in the range of 1 pf to 10 pf, is needed to prevent oscillation from the negative impedance. resistance scaling the ad5231 offers 10 k?, 50 k?, and 100 k? nominal resistance. for users who need lower resistance but want to maintain the number of adjustment steps, they can parallel multiple devices. for example, figure 54 shows a simple scheme o f paralleling two ad5231s. to adjust half the resistance linearly per step, users need to program both devices coherently with the same settings and tie the terminals as shown. a1 b1 w1 w2 a2 b2 ld 02739-053 figure 54 . reduce resistance by half with linear adj ustment cha r acteristics in voltage diver mode, by paralleling a discrete resistor as shown in figure 55 , a proportionately lower voltage appears at terminal s a C b. this translates into a finer degree of prec i sion, because the step size at terminal w is smaller. the vol t age can be found as follows: dd ab ab w v d r2 r r3 ) r2 r d v + = 1024 // // ( ) ( (10) r1 r2 a b w r3 02739-059 figure 55 . lowering the nominal resistance figure 54 and figure 55 show that the digital potentiometers change steps linearly. on the other hand, pseudo log taper adjustment is usually preferred in applications such as audio co n trol. figure 56 shows another type of resistance scaling. in this configuration, the smaller the r2 with respect to r1, the more the pseudo log taper characteristic of the circuit behaves. r1 r2 v o a b w 02739-055 figure 56 . resistor scaling with pseudo log adjustment characte r istics
ad5231 data sheet rev. d | page 26 of 28 rdac circuit simulat ion model the internal parasi tic capacitances and the external load dominates the ac characteristics of the rdacs . the ?3 db ban d width of the ad5231bru10 (10 k? resistor) measures 370 khz at half scale when configured as a potentiometer divider. figure 15 provides the large signal bode plot chara c - teristics. a parasitic simulation mode is sh own in figure 57. a rdac 10k? w b c a 50pf c b 50pf c w 50pf 02739-056 figure 57 . rdac circuit simulation model for rdac = 10 k? the following code provides a macro model net list for the 10 k? rdac: .param d = 1024, rdac = 10e3 * .subckt dpot (a, w, b) * ca a 0 50e-12 rwa a w {(1-d/1024)* rdac + 15} cw w 0 50e-12 rwb w b {d/1024 * rdac + 15} cb b 0 50e-12 * .ends dpot
data sheet ad5231 rev. d | page 27 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 58 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 r ab (k ?) temperature range package d e scription package o p tion ordering quantity ad5231bru10 10 ? 40c to +85c 16- lead tssop ru -16 96 ad5231bru10 -r eel 7 10 ? 40c to +85c 16- lead tssop ru -16 1,000 ad5231bruz1 0 10 ? 40c to +85c 16- lead tssop ru -16 96 ad5231bruz1 0- reel7 10 ? 40c to +85c 16- lead tssop ru -16 1,000 ad5231bruz5 0 50 ? 40c to +85c 16- lead tssop ru -16 96 ad5231bruz5 0- reel7 50 ? 40c to +85c 16- lead tssop ru -16 1,000 ad5231bru100 100 ? 40c to +85c 16- lead tssop ru -16 96 ad5231bru100 -r ee l7 100 ? 40 c to +85c 16- lead tssop ru -16 1,000 AD5231BRUZ100 100 ? 40c to +85c 16- lead tssop ru -16 96 AD5231BRUZ100 -r l7 100 ? 40c to +85c 16- lead tssop ru -16 1 ,000 1 z = rohs compliant part.
ad5231 data sheet rev. d | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2001C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02739-0-3/13(d)

▲Up To Search▲

Price & Availability of AD5231BRUZ10

	To Download AD5231BRUZ10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .